Espressif Systems /ESP32-P4 /SDHOST /CLKDIV

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Interpret as CLKDIV

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLK_DIVIDER00CLK_DIVIDER10CLK_DIVIDER20CLK_DIVIDER3

Description

Clock divider configuration register

Fields

CLK_DIVIDER0

Clock divider0 value. Clock divisor is 2n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 21 = 2, a value of 0xFF means divided by 2*255 = 510, and so on.

CLK_DIVIDER1

Clock divider1 value. Clock divisor is 2n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 21 = 2, a value of 0xFF means divided by 2*255 = 510, and so on.

CLK_DIVIDER2

Clock divider2 value. Clock divisor is 2n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 21 = 2, a value of 0xFF means divided by 2*255 = 510, and so on.

CLK_DIVIDER3

Clock divider3 value. Clock divisor is 2n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 21 = 2, a value of 0xFF means divided by 2*255 = 510, and so on.

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